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| CCD Delay Line Series MN38663S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38663S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 680.5 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38663S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38663S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC VSS3 VDD3 VINC1 N.C. VINVC VGC1 VO1C VDD1 VSS1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 XIV PCOUT & VCOIN -VBB VSS2 VDD2 VINVY SW VINC2 VGC2 VO2Y ( TOP VIEW ) SOP020-P-0300 Features Single 4.4 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38663S for signal processing Applications Video cameras 1 MN38663S Block Diagram CCD Delay Line Series VGC1 16 V DD2 17 V SS2 10 14 Bias circuit Clamp circuit Mode switch Booster circuit Voltage generator VINVC 6 L H 78.5-stage Charge input block Charge input block analog shift register L H 602-stage analog shift register Charge detector Voltage generator 8 VINC1 4 H L 3-stage analog shift register Resampling output amplifier 12 VO1C 11 VO2Y oS driver oR driver oSH driver Substrate bias generator 18 -VBB 3 2 9 L H VINVY 15 L H Charge input block Charge input block 78.5-stage analog shift register L H 602-stage analog shift register Charge detector VINC2 13 H L Resampling output amplifier 3-stage analog shift register L H XIV 20 L H H Waveform amplifier adjustment block 1/3rd frequency divider L XIC 1 Waveform adjustment block o1 driver L H VCO Timing adjustment L H o2 driver Phase comparator 19 VSS PCOUT & VCOIN 2 7 VGC2 VDD1 VDD3 VSS1 VSS3 SW CCD Delay Line Series Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol XIC VSS3 VDD3 VINC1 N.C. VINVC VGC1 VO1C VDD1 VSS1 VO2Y VGC2 VINC2 SW VINVY VDD2 VSS2 -VBB PCOUT&VCOIN XIV Pin Name 9.545454 MHz clock input GND (3) Power supply (3) Camera signal input (1) No connection Video signal input (C) Output gate connection (1) Signal output (1C) Power supply (1) GND (1) Signal output (2Y) Output gate connection (2) Power supply (2) Camera/video mode switch Video signal input (Y) Power supply (2) GND (2) Substrate connection Phase comparator output and voltage controlled oscillator input 3.579545 MHz clock input Notes 1: Always connect VDD1, VDD2, and VDD3 to the same voltage. 2: Always connect VSS1, VSS2, and VSS3 to ground. MN38663S Function Description Ground for clock multiplier circuit Power supply for clock multiplier circuit Output pin for signal fed to pin 4 or pin 6 Power supply for analog circuits Ground for analog circuits Output pin for signal fed to pin 13 or pin 15 Power supply for digital circuits other than frequency multiplier Ground for digital circuits other than frequency multiplier Negative voltage pin 3 MN38663S Electrical Characteristics CCD Delay Line Series VDD=4.4V, Vckv=0.3VP-P (sine wave), fckv=3.579545MHz (Converted to 10.738635 MHz internally) Vckc=0.3VP-P (sine wave), fckc=9.545454MHz, Vin=0.5VP-P (sine wave), Ta=25C Parameter Power supply current (Video signal I/O) Power supply current (Camera signal I/O) Signal bandwidth (Video signal I/O) Signal bandwidth (Camera signal I/O) Insertion gain Total harmonic distortion Signal-to-noise ratio Clock leak (V1) Clock leak (C) Clock leak (V2) Crosstalk Delay (Video signal I/O) Delay (Camera signal I/O) VO pin output impedance Input bias voltage Input bias voltage Input clamp voltage Output bias voltage Output bias voltage Output clamp voltage Substrate voltage Symbol IDDV IDDC BWV BWC IG THD S/N NCV1 NCC NCV2 CT DV DC ZO VBINC VBINY VCLIN VBOC VBOY VCLO -VBB Applicable to signal input pins VINC1 and VINC2 Applicable to signal input pin VINC1 Applicable to signal input pin VINVY Applicable to signal output pins VO1C and VO2Y when SW is "H" level Applicable to signal output pin VO1C when SW is "L" level Applicable to signal output pin VO2Y when SW is "L" level 2.20 2.10 1.90 1.30 1.35 1.05 Conditions Average current for 4.4-V power supply when SW is "L" level Average current for 4.4-V power supply when SW is "H" level -3 dB for 200 kHz value when SW is "L" level -3 dB for 200 kHz value when SW is "H" level fsig=200kHz fsig=200kHz Signal output (VP-P)/noise output (rms) 3.579545-MHz component output/main output signal when SW is "L" level 9.545454-MHz component output/main output signal when SW is "H" level 10.738635-MHz component output/main output signal when switch signal is "L" level fsig=200kHz When SW is "L" level When SW is "H" level 63.40 63.42 350 2.50 2.40 2.20 2.30 2.35 2.05 -2.5 700 2.80 2.70 2.50 3.30 3.35 3.05 -37 dB s V V V V V V V 50 3.0 2.7 1 min typ 30 28 4.2 MHz 3.7 4 1 56 -50 -15 -15 -40 -10 -10 7 4 dB % dB dB dB dB max 48 mA 46 Unit 4 CCD Delay Line Series Application Circuit Example MN38663S + 4.4V - 10m 4.4V or GND 0.01F VGC1 0.01F 12 VGC2 0.1F VDD1 16 VDD2 10 VSS1 0.1F 17 VSS2 VDD3 0.1F VSS3 14 SW 3 2 9 Bias circuit Clamp circuit Mode switch Booster circuit 7 Voltage generator Signal input VINVC 6 -+ 0.47F Signal input VINC1 4 -+ 0.47F Signal input VINVY 15 -+ 0.47F Signal input VINC2 13 -+ 0.47F Clock input XIV 20 1000pF Clock input XIC 1 L H H L 78.5-stage Charge input block Charge input block analog shift register L H 602-stage analog shift register Charge detector Voltage generator 8 VO1C Signal output (1C) 3-stage analog shift register Resampling output amplifier L H L H H L L 78.5-stage Charge input block Charge input block analog shift register L H 602-stage analog shift register Charge detector Resampling output amplifier 11 VO2Y Signal output (2Y) 3-stage analog shift register L H oS driver H H Waveform amplifier adjustment block 1/3rd frequency divider L Waveform adjustment block o1 driver oR driver 1000pF oSH driver VCO Timing adjustment L H PCOUT & VCOIN 19 o2 driver L H Phase comparator Substrate bias generator -VBB 18 0.01F 0.01F 820 1000pF Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 5 MN38663S Package Dimensions (Unit:mm) SOP020-P-0300 CCD Delay Line Series 12.600.20 20 11 1.100.20 5.500.20 7.700.30 0.15 -0.05 +0.10 0 to 10 0.30min. 1 10 1.90max. 1.500.20 (0.6) 1.27 0.400.10 SEATING PLANE 6 0.100.10 |
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